wyvernSemi
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Cambridge, United Kingdom
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{
"name": "pcievhost",
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{
"name": "usbModel",
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{
"name": "tcpIpPg",
"description": "10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL",
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{
"name": "rv32",
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"\n <div class=\"d-flex width-full position-relative\">\n <div class=\"flex-1\">\n <svg aria-hidden=\"true\" data-component=\"Octicon\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo mr-1 tmp-mr-1 color-fg-muted\">\n <path d=\"M2 2.5A2.5 2.5 0 0 1 4.5 0h8.75a.75.75 0 0 1 .75.75v12.5a.75.75 0 0 1-.75.75h-2.5a.75.75 0 0 1 0-1.5h1.75v-2h-8a1 1 0 0 0-.714 1.7.75.75 0 1 1-1.072 1.05A2.495 2.495 0 0 1 2 11.5Zm10.5-1h-8a1 1 0 0 0-1 1v6.708A2.486 2.486 0 0 1 4.5 9h8ZM5 12.25a.25.25 0 0 1 .25-.25h3.5a.25.25 0 0 1 .25.25v3.25a.25.25 0 0 1-.4.2l-1.45-1.087a.249.249 0 0 0-.3 0L5.4 15.7a.25.25 0 0 1-.4-.2Z\"></path>\n</svg>\n <span data-view-component=\"true\" class=\"position-relative\"><a data-hydro-click=\"{"event_type":"user_profile.click","payload":{"profile_user_id":21970031,"target":"PINNED_REPO","user_id":null,"originating_url":"https://github.com/wyvernSemi"}}\" data-hydro-click-hmac=\"2a6a229f89de0a3685da72a04f1e1ec504a6b98567e8a86748d96f9b439228b6\" id=\"70256088\" href=\"/wyvernSemi/pcievhost\" data-view-component=\"true\" class=\"Link mr-1 tmp-mr-1 text-bold wb-break-word\"><span class=\"repo\">pcievhost</span></a> <tool-tip data-direction=\"n\" id=\"tooltip-192cfae4-5e75-4fe3-a9ca-7fb1d15a50ca\" for=\"70256088\" popover=\"manual\" data-type=\"label\" data-view-component=\"true\" class=\"sr-only position-absolute\">pcievhost</tool-tip></span> <span></span><span class=\"Label Label--secondary v-align-middle mt-1 no-wrap v-align-baseline Label--inline\">Public</span>\n </div>\n </div>\n\n\n <p class=\"pinned-item-desc color-fg-muted text-small mt-2 mb-0\">\n PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities\n </p>\n\n <p class=\"mb-0 mt-2 f6 color-fg-muted\">\n <span class=\"tmp-mr-3 d-inline-block\">\n <span class=\"repo-language-color\" style=\"background-color: #555555\"></span>\n <span itemprop=\"programmingLanguage\">C</span>\n</span>\n\n <a href=\"/wyvernSemi/pcievhost/stargazers\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"stars\" role=\"img\" data-component=\"Octicon\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-star\">\n <path d=\"M8 .25a.75.75 0 0 1 .673.418l1.882 3.815 4.21.612a.75.75 0 0 1 .416 1.279l-3.046 2.97.719 4.192a.751.751 0 0 1-1.088.791L8 12.347l-3.766 1.98a.75.75 0 0 1-1.088-.79l.72-4.194L.818 6.374a.75.75 0 0 1 .416-1.28l4.21-.611L7.327.668A.75.75 0 0 1 8 .25Zm0 2.445L6.615 5.5a.75.75 0 0 1-.564.41l-3.097.45 2.24 2.184a.75.75 0 0 1 .216.664l-.528 3.084 2.769-1.456a.75.75 0 0 1 .698 0l2.77 1.456-.53-3.084a.75.75 0 0 1 .216-.664l2.24-2.183-3.096-.45a.75.75 0 0 1-.564-.41L8 2.694Z\"></path>\n</svg>\n 148\n </a>\n <a href=\"/wyvernSemi/pcievhost/forks\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"forks\" role=\"img\" data-component=\"Octicon\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo-forked\">\n <path d=\"M5 5.372v.878c0 .414.336.75.75.75h4.5a.75.75 0 0 0 .75-.75v-.878a2.25 2.25 0 1 1 1.5 0v.878a2.25 2.25 0 0 1-2.25 2.25h-1.5v2.128a2.251 2.251 0 1 1-1.5 0V8.5h-1.5A2.25 2.25 0 0 1 3.5 6.25v-.878a2.25 2.25 0 1 1 1.5 0ZM5 3.25a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Zm6.75.75a.75.75 0 1 0 0-1.5.75.75 0 0 0 0 1.5Zm-3 8.75a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Z\"></path>\n</svg>\n 35\n </a>\n </p>\n ",
"\n <div class=\"d-flex width-full position-relative\">\n <div class=\"flex-1\">\n <svg aria-hidden=\"true\" data-component=\"Octicon\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo mr-1 tmp-mr-1 color-fg-muted\">\n <path d=\"M2 2.5A2.5 2.5 0 0 1 4.5 0h8.75a.75.75 0 0 1 .75.75v12.5a.75.75 0 0 1-.75.75h-2.5a.75.75 0 0 1 0-1.5h1.75v-2h-8a1 1 0 0 0-.714 1.7.75.75 0 1 1-1.072 1.05A2.495 2.495 0 0 1 2 11.5Zm10.5-1h-8a1 1 0 0 0-1 1v6.708A2.486 2.486 0 0 1 4.5 9h8ZM5 12.25a.25.25 0 0 1 .25-.25h3.5a.25.25 0 0 1 .25.25v3.25a.25.25 0 0 1-.4.2l-1.45-1.087a.249.249 0 0 0-.3 0L5.4 15.7a.25.25 0 0 1-.4-.2Z\"></path>\n</svg>\n <span data-view-component=\"true\" class=\"position-relative\"><a data-hydro-click=\"{"event_type":"user_profile.click","payload":{"profile_user_id":21970031,"target":"PINNED_REPO","user_id":null,"originating_url":"https://github.com/wyvernSemi"}}\" data-hydro-click-hmac=\"2a6a229f89de0a3685da72a04f1e1ec504a6b98567e8a86748d96f9b439228b6\" id=\"69550177\" href=\"/wyvernSemi/vproc\" data-view-component=\"true\" class=\"Link mr-1 tmp-mr-1 text-bold wb-break-word\"><span class=\"repo\">vproc</span></a> <tool-tip data-direction=\"n\" id=\"tooltip-0bf8cafa-83ea-44f1-af03-4a013b1bf750\" for=\"69550177\" popover=\"manual\" data-type=\"label\" data-view-component=\"true\" class=\"sr-only position-absolute\">vproc</tool-tip></span> <span></span><span class=\"Label Label--secondary v-align-middle mt-1 no-wrap v-align-baseline Label--inline\">Public</span>\n </div>\n </div>\n\n\n <p class=\"pinned-item-desc color-fg-muted text-small mt-2 mb-0\">\n Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus\n </p>\n\n <p class=\"mb-0 mt-2 f6 color-fg-muted\">\n <span class=\"tmp-mr-3 d-inline-block\">\n <span class=\"repo-language-color\" style=\"background-color: #adb2cb\"></span>\n <span itemprop=\"programmingLanguage\">VHDL</span>\n</span>\n\n <a href=\"/wyvernSemi/vproc/stargazers\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"stars\" role=\"img\" data-component=\"Octicon\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-star\">\n <path d=\"M8 .25a.75.75 0 0 1 .673.418l1.882 3.815 4.21.612a.75.75 0 0 1 .416 1.279l-3.046 2.97.719 4.192a.751.751 0 0 1-1.088.791L8 12.347l-3.766 1.98a.75.75 0 0 1-1.088-.79l.72-4.194L.818 6.374a.75.75 0 0 1 .416-1.28l4.21-.611L7.327.668A.75.75 0 0 1 8 .25Zm0 2.445L6.615 5.5a.75.75 0 0 1-.564.41l-3.097.45 2.24 2.184a.75.75 0 0 1 .216.664l-.528 3.084 2.769-1.456a.75.75 0 0 1 .698 0l2.77 1.456-.53-3.084a.75.75 0 0 1 .216-.664l2.24-2.183-3.096-.45a.75.75 0 0 1-.564-.41L8 2.694Z\"></path>\n</svg>\n 76\n </a>\n <a href=\"/wyvernSemi/vproc/forks\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"forks\" role=\"img\" data-component=\"Octicon\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo-forked\">\n <path d=\"M5 5.372v.878c0 .414.336.75.75.75h4.5a.75.75 0 0 0 .75-.75v-.878a2.25 2.25 0 1 1 1.5 0v.878a2.25 2.25 0 0 1-2.25 2.25h-1.5v2.128a2.251 2.251 0 1 1-1.5 0V8.5h-1.5A2.25 2.25 0 0 1 3.5 6.25v-.878a2.25 2.25 0 1 1 1.5 0ZM5 3.25a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Zm6.75.75a.75.75 0 1 0 0-1.5.75.75 0 0 0 0 1.5Zm-3 8.75a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Z\"></path>\n</svg>\n 14\n </a>\n </p>\n ",
"\n <div class=\"d-flex width-full position-relative\">\n <div class=\"flex-1\">\n <svg aria-hidden=\"true\" data-component=\"Octicon\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo mr-1 tmp-mr-1 color-fg-muted\">\n <path d=\"M2 2.5A2.5 2.5 0 0 1 4.5 0h8.75a.75.75 0 0 1 .75.75v12.5a.75.75 0 0 1-.75.75h-2.5a.75.75 0 0 1 0-1.5h1.75v-2h-8a1 1 0 0 0-.714 1.7.75.75 0 1 1-1.072 1.05A2.495 2.495 0 0 1 2 11.5Zm10.5-1h-8a1 1 0 0 0-1 1v6.708A2.486 2.486 0 0 1 4.5 9h8ZM5 12.25a.25.25 0 0 1 .25-.25h3.5a.25.25 0 0 1 .25.25v3.25a.25.25 0 0 1-.4.2l-1.45-1.087a.249.249 0 0 0-.3 0L5.4 15.7a.25.25 0 0 1-.4-.2Z\"></path>\n</svg>\n <span data-view-component=\"true\" class=\"position-relative\"><a data-hydro-click=\"{"event_type":"user_profile.click","payload":{"profile_user_id":21970031,"target":"PINNED_REPO","user_id":null,"originating_url":"https://github.com/wyvernSemi"}}\" data-hydro-click-hmac=\"2a6a229f89de0a3685da72a04f1e1ec504a6b98567e8a86748d96f9b439228b6\" id=\"711933491\" href=\"/wyvernSemi/usbModel\" data-view-component=\"true\" class=\"Link mr-1 tmp-mr-1 text-bold wb-break-word\"><span class=\"repo\">usbModel</span></a> <tool-tip data-direction=\"n\" id=\"tooltip-4cb51634-0a1f-49be-9b12-9fae469eb837\" for=\"711933491\" popover=\"manual\" data-type=\"label\" data-view-component=\"true\" class=\"sr-only position-absolute\">usbModel</tool-tip></span> <span></span><span class=\"Label Label--secondary v-align-middle mt-1 no-wrap v-align-baseline Label--inline\">Public</span>\n </div>\n </div>\n\n\n <p class=\"pinned-item-desc color-fg-muted text-small mt-2 mb-0\">\n USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL\n </p>\n\n <p class=\"mb-0 mt-2 f6 color-fg-muted\">\n <span class=\"tmp-mr-3 d-inline-block\">\n <span class=\"repo-language-color\" style=\"background-color: #f34b7d\"></span>\n <span itemprop=\"programmingLanguage\">C++</span>\n</span>\n\n <a href=\"/wyvernSemi/usbModel/stargazers\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"stars\" role=\"img\" data-component=\"Octicon\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-star\">\n <path d=\"M8 .25a.75.75 0 0 1 .673.418l1.882 3.815 4.21.612a.75.75 0 0 1 .416 1.279l-3.046 2.97.719 4.192a.751.751 0 0 1-1.088.791L8 12.347l-3.766 1.98a.75.75 0 0 1-1.088-.79l.72-4.194L.818 6.374a.75.75 0 0 1 .416-1.28l4.21-.611L7.327.668A.75.75 0 0 1 8 .25Zm0 2.445L6.615 5.5a.75.75 0 0 1-.564.41l-3.097.45 2.24 2.184a.75.75 0 0 1 .216.664l-.528 3.084 2.769-1.456a.75.75 0 0 1 .698 0l2.77 1.456-.53-3.084a.75.75 0 0 1 .216-.664l2.24-2.183-3.096-.45a.75.75 0 0 1-.564-.41L8 2.694Z\"></path>\n</svg>\n 35\n </a>\n <a href=\"/wyvernSemi/usbModel/forks\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"forks\" role=\"img\" data-component=\"Octicon\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo-forked\">\n <path d=\"M5 5.372v.878c0 .414.336.75.75.75h4.5a.75.75 0 0 0 .75-.75v-.878a2.25 2.25 0 1 1 1.5 0v.878a2.25 2.25 0 0 1-2.25 2.25h-1.5v2.128a2.251 2.251 0 1 1-1.5 0V8.5h-1.5A2.25 2.25 0 0 1 3.5 6.25v-.878a2.25 2.25 0 1 1 1.5 0ZM5 3.25a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Zm6.75.75a.75.75 0 1 0 0-1.5.75.75 0 0 0 0 1.5Zm-3 8.75a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Z\"></path>\n</svg>\n 4\n </a>\n </p>\n ",
"\n <div class=\"d-flex width-full position-relative\">\n <div class=\"flex-1\">\n <svg aria-hidden=\"true\" data-component=\"Octicon\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo mr-1 tmp-mr-1 color-fg-muted\">\n <path d=\"M2 2.5A2.5 2.5 0 0 1 4.5 0h8.75a.75.75 0 0 1 .75.75v12.5a.75.75 0 0 1-.75.75h-2.5a.75.75 0 0 1 0-1.5h1.75v-2h-8a1 1 0 0 0-.714 1.7.75.75 0 1 1-1.072 1.05A2.495 2.495 0 0 1 2 11.5Zm10.5-1h-8a1 1 0 0 0-1 1v6.708A2.486 2.486 0 0 1 4.5 9h8ZM5 12.25a.25.25 0 0 1 .25-.25h3.5a.25.25 0 0 1 .25.25v3.25a.25.25 0 0 1-.4.2l-1.45-1.087a.249.249 0 0 0-.3 0L5.4 15.7a.25.25 0 0 1-.4-.2Z\"></path>\n</svg>\n <span data-view-component=\"true\" class=\"position-relative\"><a data-hydro-click=\"{"event_type":"user_profile.click","payload":{"profile_user_id":21970031,"target":"PINNED_REPO","user_id":null,"originating_url":"https://github.com/wyvernSemi"}}\" data-hydro-click-hmac=\"2a6a229f89de0a3685da72a04f1e1ec504a6b98567e8a86748d96f9b439228b6\" id=\"400732037\" href=\"/wyvernSemi/tcpIpPg\" data-view-component=\"true\" class=\"Link mr-1 tmp-mr-1 text-bold wb-break-word\"><span class=\"repo\">tcpIpPg</span></a> <tool-tip data-direction=\"n\" id=\"tooltip-a86932ef-8953-4637-b861-5a657847d666\" for=\"400732037\" popover=\"manual\" data-type=\"label\" data-view-component=\"true\" class=\"sr-only position-absolute\">tcpIpPg</tool-tip></span> <span></span><span class=\"Label Label--secondary v-align-middle mt-1 no-wrap v-align-baseline Label--inline\">Public</span>\n </div>\n </div>\n\n\n <p class=\"pinned-item-desc color-fg-muted text-small mt-2 mb-0\">\n 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL\n </p>\n\n <p class=\"mb-0 mt-2 f6 color-fg-muted\">\n <span class=\"tmp-mr-3 d-inline-block\">\n <span class=\"repo-language-color\" style=\"background-color: #f34b7d\"></span>\n <span itemprop=\"programmingLanguage\">C++</span>\n</span>\n\n <a href=\"/wyvernSemi/tcpIpPg/stargazers\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"stars\" role=\"img\" data-component=\"Octicon\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-star\">\n <path d=\"M8 .25a.75.75 0 0 1 .673.418l1.882 3.815 4.21.612a.75.75 0 0 1 .416 1.279l-3.046 2.97.719 4.192a.751.751 0 0 1-1.088.791L8 12.347l-3.766 1.98a.75.75 0 0 1-1.088-.79l.72-4.194L.818 6.374a.75.75 0 0 1 .416-1.28l4.21-.611L7.327.668A.75.75 0 0 1 8 .25Zm0 2.445L6.615 5.5a.75.75 0 0 1-.564.41l-3.097.45 2.24 2.184a.75.75 0 0 1 .216.664l-.528 3.084 2.769-1.456a.75.75 0 0 1 .698 0l2.77 1.456-.53-3.084a.75.75 0 0 1 .216-.664l2.24-2.183-3.096-.45a.75.75 0 0 1-.564-.41L8 2.694Z\"></path>\n</svg>\n 29\n </a>\n <a href=\"/wyvernSemi/tcpIpPg/forks\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"forks\" role=\"img\" data-component=\"Octicon\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo-forked\">\n <path d=\"M5 5.372v.878c0 .414.336.75.75.75h4.5a.75.75 0 0 0 .75-.75v-.878a2.25 2.25 0 1 1 1.5 0v.878a2.25 2.25 0 0 1-2.25 2.25h-1.5v2.128a2.251 2.251 0 1 1-1.5 0V8.5h-1.5A2.25 2.25 0 0 1 3.5 6.25v-.878a2.25 2.25 0 1 1 1.5 0ZM5 3.25a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Zm6.75.75a.75.75 0 1 0 0-1.5.75.75 0 0 0 0 1.5Zm-3 8.75a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Z\"></path>\n</svg>\n 5\n </a>\n </p>\n ",
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