WangXuan95
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Univ. of Sci. & Tech. of China (USTC)
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"name": "Dr.W.X",
"username": "WangXuan95",
"description": "PhD graduated from USTC // FPGA // Verilog // Data Compression // LLM newbie // Hope to bring better open source projects. Welcome to report bugs.",
"location": "China",
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{
"name": "FPGA-USB-Device",
"description": "An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…",
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{
"name": "FPGA-FOC",
"description": "An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。",
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{
"name": "FPGA-Gzip-compressor",
"description": "An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据，输出标准的GZIP格式，即常见的 .gz / .tar.gz 文件的格式。",
"language": ""
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{
"name": "FPGA-JPEG-LS-encoder",
"description": "An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。",
"language": ""
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{
"name": "BSV_Tutorial_cn",
"description": "一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。",
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{
"name": "NBLI",
"description": "NBLI is a fast, better lossless image compression algorithm. The optimized version (fNBLI) can get 1.5x compression ratio, 8x faster encoding, and 1.2x faster decoding compared to PNG. It can also …",
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"\n <div class=\"d-flex width-full position-relative\">\n <div class=\"flex-1\">\n <svg aria-hidden=\"true\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo mr-1 color-fg-muted\">\n <path d=\"M2 2.5A2.5 2.5 0 0 1 4.5 0h8.75a.75.75 0 0 1 .75.75v12.5a.75.75 0 0 1-.75.75h-2.5a.75.75 0 0 1 0-1.5h1.75v-2h-8a1 1 0 0 0-.714 1.7.75.75 0 1 1-1.072 1.05A2.495 2.495 0 0 1 2 11.5Zm10.5-1h-8a1 1 0 0 0-1 1v6.708A2.486 2.486 0 0 1 4.5 9h8ZM5 12.25a.25.25 0 0 1 .25-.25h3.5a.25.25 0 0 1 .25.25v3.25a.25.25 0 0 1-.4.2l-1.45-1.087a.249.249 0 0 0-.3 0L5.4 15.7a.25.25 0 0 1-.4-.2Z\"></path>\n</svg>\n <span data-view-component=\"true\" class=\"position-relative\"><a data-hydro-click=\"{"event_type":"user_profile.click","payload":{"profile_user_id":20251744,"target":"PINNED_REPO","user_id":null,"originating_url":"https://github.com/WangXuan95"}}\" data-hydro-click-hmac=\"c81d2086fd934b5d3ed98bd3a15ac14ed0c4b8cdc9802ffa4ba66e381266e1cd\" id=\"292806830\" href=\"/WangXuan95/FPGA-USB-Device\" data-view-component=\"true\" class=\"Link mr-1 text-bold wb-break-word\"><span class=\"repo\">FPGA-USB-Device</span></a> <tool-tip data-direction=\"n\" id=\"tooltip-d54ba87d-0df2-45f7-b9ee-ee0ac4d1151d\" for=\"292806830\" popover=\"manual\" data-type=\"label\" data-view-component=\"true\" class=\"sr-only position-absolute\">FPGA-USB-Device</tool-tip></span> <span></span><span class=\"Label Label--secondary v-align-middle mt-1 no-wrap v-align-baseline Label--inline\">Public</span>\n </div>\n </div>\n\n\n <p class=\"pinned-item-desc color-fg-muted text-small mt-2 mb-0\">\n An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…\n </p>\n\n <p class=\"mb-0 mt-2 f6 color-fg-muted\">\n <span class=\"tmp-mr-3 d-inline-block\">\n <span class=\"repo-language-color\" style=\"background-color: #b2b7f8\"></span>\n <span itemprop=\"programmingLanguage\">Verilog</span>\n</span>\n\n <a href=\"/WangXuan95/FPGA-USB-Device/stargazers\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"stars\" role=\"img\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-star\">\n <path d=\"M8 .25a.75.75 0 0 1 .673.418l1.882 3.815 4.21.612a.75.75 0 0 1 .416 1.279l-3.046 2.97.719 4.192a.751.751 0 0 1-1.088.791L8 12.347l-3.766 1.98a.75.75 0 0 1-1.088-.79l.72-4.194L.818 6.374a.75.75 0 0 1 .416-1.28l4.21-.611L7.327.668A.75.75 0 0 1 8 .25Zm0 2.445L6.615 5.5a.75.75 0 0 1-.564.41l-3.097.45 2.24 2.184a.75.75 0 0 1 .216.664l-.528 3.084 2.769-1.456a.75.75 0 0 1 .698 0l2.77 1.456-.53-3.084a.75.75 0 0 1 .216-.664l2.24-2.183-3.096-.45a.75.75 0 0 1-.564-.41L8 2.694Z\"></path>\n</svg>\n 865\n </a>\n <a href=\"/WangXuan95/FPGA-USB-Device/forks\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"forks\" role=\"img\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo-forked\">\n <path d=\"M5 5.372v.878c0 .414.336.75.75.75h4.5a.75.75 0 0 0 .75-.75v-.878a2.25 2.25 0 1 1 1.5 0v.878a2.25 2.25 0 0 1-2.25 2.25h-1.5v2.128a2.251 2.251 0 1 1-1.5 0V8.5h-1.5A2.25 2.25 0 0 1 3.5 6.25v-.878a2.25 2.25 0 1 1 1.5 0ZM5 3.25a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Zm6.75.75a.75.75 0 1 0 0-1.5.75.75 0 0 0 0 1.5Zm-3 8.75a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Z\"></path>\n</svg>\n 146\n </a>\n </p>\n ",
"\n <div class=\"d-flex width-full position-relative\">\n <div class=\"flex-1\">\n <svg aria-hidden=\"true\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo mr-1 color-fg-muted\">\n <path d=\"M2 2.5A2.5 2.5 0 0 1 4.5 0h8.75a.75.75 0 0 1 .75.75v12.5a.75.75 0 0 1-.75.75h-2.5a.75.75 0 0 1 0-1.5h1.75v-2h-8a1 1 0 0 0-.714 1.7.75.75 0 1 1-1.072 1.05A2.495 2.495 0 0 1 2 11.5Zm10.5-1h-8a1 1 0 0 0-1 1v6.708A2.486 2.486 0 0 1 4.5 9h8ZM5 12.25a.25.25 0 0 1 .25-.25h3.5a.25.25 0 0 1 .25.25v3.25a.25.25 0 0 1-.4.2l-1.45-1.087a.249.249 0 0 0-.3 0L5.4 15.7a.25.25 0 0 1-.4-.2Z\"></path>\n</svg>\n <span data-view-component=\"true\" class=\"position-relative\"><a data-hydro-click=\"{"event_type":"user_profile.click","payload":{"profile_user_id":20251744,"target":"PINNED_REPO","user_id":null,"originating_url":"https://github.com/WangXuan95"}}\" data-hydro-click-hmac=\"c81d2086fd934b5d3ed98bd3a15ac14ed0c4b8cdc9802ffa4ba66e381266e1cd\" id=\"341099147\" href=\"/WangXuan95/FPGA-FOC\" data-view-component=\"true\" class=\"Link mr-1 text-bold wb-break-word\"><span class=\"repo\">FPGA-FOC</span></a> <tool-tip data-direction=\"n\" id=\"tooltip-a1849f01-eb66-4d27-bc68-e24ed197f99b\" for=\"341099147\" popover=\"manual\" data-type=\"label\" data-view-component=\"true\" class=\"sr-only position-absolute\">FPGA-FOC</tool-tip></span> <span></span><span class=\"Label Label--secondary v-align-middle mt-1 no-wrap v-align-baseline Label--inline\">Public</span>\n </div>\n </div>\n\n\n <p class=\"pinned-item-desc color-fg-muted text-small mt-2 mb-0\">\n An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。\n </p>\n\n <p class=\"mb-0 mt-2 f6 color-fg-muted\">\n <span class=\"tmp-mr-3 d-inline-block\">\n <span class=\"repo-language-color\" style=\"background-color: #b2b7f8\"></span>\n <span itemprop=\"programmingLanguage\">Verilog</span>\n</span>\n\n <a href=\"/WangXuan95/FPGA-FOC/stargazers\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"stars\" role=\"img\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-star\">\n <path d=\"M8 .25a.75.75 0 0 1 .673.418l1.882 3.815 4.21.612a.75.75 0 0 1 .416 1.279l-3.046 2.97.719 4.192a.751.751 0 0 1-1.088.791L8 12.347l-3.766 1.98a.75.75 0 0 1-1.088-.79l.72-4.194L.818 6.374a.75.75 0 0 1 .416-1.28l4.21-.611L7.327.668A.75.75 0 0 1 8 .25Zm0 2.445L6.615 5.5a.75.75 0 0 1-.564.41l-3.097.45 2.24 2.184a.75.75 0 0 1 .216.664l-.528 3.084 2.769-1.456a.75.75 0 0 1 .698 0l2.77 1.456-.53-3.084a.75.75 0 0 1 .216-.664l2.24-2.183-3.096-.45a.75.75 0 0 1-.564-.41L8 2.694Z\"></path>\n</svg>\n 847\n </a>\n <a href=\"/WangXuan95/FPGA-FOC/forks\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"forks\" role=\"img\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo-forked\">\n <path d=\"M5 5.372v.878c0 .414.336.75.75.75h4.5a.75.75 0 0 0 .75-.75v-.878a2.25 2.25 0 1 1 1.5 0v.878a2.25 2.25 0 0 1-2.25 2.25h-1.5v2.128a2.251 2.251 0 1 1-1.5 0V8.5h-1.5A2.25 2.25 0 0 1 3.5 6.25v-.878a2.25 2.25 0 1 1 1.5 0ZM5 3.25a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Zm6.75.75a.75.75 0 1 0 0-1.5.75.75 0 0 0 0 1.5Zm-3 8.75a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Z\"></path>\n</svg>\n 245\n </a>\n </p>\n ",
"\n <div class=\"d-flex width-full position-relative\">\n <div class=\"flex-1\">\n <svg aria-hidden=\"true\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo mr-1 color-fg-muted\">\n <path d=\"M2 2.5A2.5 2.5 0 0 1 4.5 0h8.75a.75.75 0 0 1 .75.75v12.5a.75.75 0 0 1-.75.75h-2.5a.75.75 0 0 1 0-1.5h1.75v-2h-8a1 1 0 0 0-.714 1.7.75.75 0 1 1-1.072 1.05A2.495 2.495 0 0 1 2 11.5Zm10.5-1h-8a1 1 0 0 0-1 1v6.708A2.486 2.486 0 0 1 4.5 9h8ZM5 12.25a.25.25 0 0 1 .25-.25h3.5a.25.25 0 0 1 .25.25v3.25a.25.25 0 0 1-.4.2l-1.45-1.087a.249.249 0 0 0-.3 0L5.4 15.7a.25.25 0 0 1-.4-.2Z\"></path>\n</svg>\n <span data-view-component=\"true\" class=\"position-relative\"><a data-hydro-click=\"{"event_type":"user_profile.click","payload":{"profile_user_id":20251744,"target":"PINNED_REPO","user_id":null,"originating_url":"https://github.com/WangXuan95"}}\" data-hydro-click-hmac=\"c81d2086fd934b5d3ed98bd3a15ac14ed0c4b8cdc9802ffa4ba66e381266e1cd\" id=\"645781763\" href=\"/WangXuan95/FPGA-Gzip-compressor\" data-view-component=\"true\" class=\"Link mr-1 text-bold wb-break-word\"><span class=\"repo\">FPGA-Gzip-compressor</span></a> <tool-tip data-direction=\"n\" id=\"tooltip-494b5181-9f6f-4d4d-a628-c1c41e87c53b\" for=\"645781763\" popover=\"manual\" data-type=\"label\" data-view-component=\"true\" class=\"sr-only position-absolute\">FPGA-Gzip-compressor</tool-tip></span> <span></span><span class=\"Label Label--secondary v-align-middle mt-1 no-wrap v-align-baseline Label--inline\">Public</span>\n </div>\n </div>\n\n\n <p class=\"pinned-item-desc color-fg-muted text-small mt-2 mb-0\">\n An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据，输出标准的GZIP格式，即常见的 .gz / .tar.gz 文件的格式。\n </p>\n\n <p class=\"mb-0 mt-2 f6 color-fg-muted\">\n <span class=\"tmp-mr-3 d-inline-block\">\n <span class=\"repo-language-color\" style=\"background-color: #b2b7f8\"></span>\n <span itemprop=\"programmingLanguage\">Verilog</span>\n</span>\n\n <a href=\"/WangXuan95/FPGA-Gzip-compressor/stargazers\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"stars\" role=\"img\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-star\">\n <path d=\"M8 .25a.75.75 0 0 1 .673.418l1.882 3.815 4.21.612a.75.75 0 0 1 .416 1.279l-3.046 2.97.719 4.192a.751.751 0 0 1-1.088.791L8 12.347l-3.766 1.98a.75.75 0 0 1-1.088-.79l.72-4.194L.818 6.374a.75.75 0 0 1 .416-1.28l4.21-.611L7.327.668A.75.75 0 0 1 8 .25Zm0 2.445L6.615 5.5a.75.75 0 0 1-.564.41l-3.097.45 2.24 2.184a.75.75 0 0 1 .216.664l-.528 3.084 2.769-1.456a.75.75 0 0 1 .698 0l2.77 1.456-.53-3.084a.75.75 0 0 1 .216-.664l2.24-2.183-3.096-.45a.75.75 0 0 1-.564-.41L8 2.694Z\"></path>\n</svg>\n 152\n </a>\n <a href=\"/WangXuan95/FPGA-Gzip-compressor/forks\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"forks\" role=\"img\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo-forked\">\n <path d=\"M5 5.372v.878c0 .414.336.75.75.75h4.5a.75.75 0 0 0 .75-.75v-.878a2.25 2.25 0 1 1 1.5 0v.878a2.25 2.25 0 0 1-2.25 2.25h-1.5v2.128a2.251 2.251 0 1 1-1.5 0V8.5h-1.5A2.25 2.25 0 0 1 3.5 6.25v-.878a2.25 2.25 0 1 1 1.5 0ZM5 3.25a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Zm6.75.75a.75.75 0 1 0 0-1.5.75.75 0 0 0 0 1.5Zm-3 8.75a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Z\"></path>\n</svg>\n 35\n </a>\n </p>\n ",
"\n <div class=\"d-flex width-full position-relative\">\n <div class=\"flex-1\">\n <svg aria-hidden=\"true\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo mr-1 color-fg-muted\">\n <path d=\"M2 2.5A2.5 2.5 0 0 1 4.5 0h8.75a.75.75 0 0 1 .75.75v12.5a.75.75 0 0 1-.75.75h-2.5a.75.75 0 0 1 0-1.5h1.75v-2h-8a1 1 0 0 0-.714 1.7.75.75 0 1 1-1.072 1.05A2.495 2.495 0 0 1 2 11.5Zm10.5-1h-8a1 1 0 0 0-1 1v6.708A2.486 2.486 0 0 1 4.5 9h8ZM5 12.25a.25.25 0 0 1 .25-.25h3.5a.25.25 0 0 1 .25.25v3.25a.25.25 0 0 1-.4.2l-1.45-1.087a.249.249 0 0 0-.3 0L5.4 15.7a.25.25 0 0 1-.4-.2Z\"></path>\n</svg>\n <span data-view-component=\"true\" class=\"position-relative\"><a data-hydro-click=\"{"event_type":"user_profile.click","payload":{"profile_user_id":20251744,"target":"PINNED_REPO","user_id":null,"originating_url":"https://github.com/WangXuan95"}}\" data-hydro-click-hmac=\"c81d2086fd934b5d3ed98bd3a15ac14ed0c4b8cdc9802ffa4ba66e381266e1cd\" id=\"272697006\" href=\"/WangXuan95/FPGA-JPEG-LS-encoder\" data-view-component=\"true\" class=\"Link mr-1 text-bold wb-break-word\"><span class=\"repo\">FPGA-JPEG-LS-encoder</span></a> <tool-tip data-direction=\"n\" id=\"tooltip-8625dfe3-945e-48db-9933-b4e0b1d2bee8\" for=\"272697006\" popover=\"manual\" data-type=\"label\" data-view-component=\"true\" class=\"sr-only position-absolute\">FPGA-JPEG-LS-encoder</tool-tip></span> <span></span><span class=\"Label Label--secondary v-align-middle mt-1 no-wrap v-align-baseline Label--inline\">Public</span>\n </div>\n </div>\n\n\n <p class=\"pinned-item-desc color-fg-muted text-small mt-2 mb-0\">\n An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。\n </p>\n\n <p class=\"mb-0 mt-2 f6 color-fg-muted\">\n <span class=\"tmp-mr-3 d-inline-block\">\n <span class=\"repo-language-color\" style=\"background-color: #b2b7f8\"></span>\n <span itemprop=\"programmingLanguage\">Verilog</span>\n</span>\n\n <a href=\"/WangXuan95/FPGA-JPEG-LS-encoder/stargazers\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"stars\" role=\"img\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-star\">\n <path d=\"M8 .25a.75.75 0 0 1 .673.418l1.882 3.815 4.21.612a.75.75 0 0 1 .416 1.279l-3.046 2.97.719 4.192a.751.751 0 0 1-1.088.791L8 12.347l-3.766 1.98a.75.75 0 0 1-1.088-.79l.72-4.194L.818 6.374a.75.75 0 0 1 .416-1.28l4.21-.611L7.327.668A.75.75 0 0 1 8 .25Zm0 2.445L6.615 5.5a.75.75 0 0 1-.564.41l-3.097.45 2.24 2.184a.75.75 0 0 1 .216.664l-.528 3.084 2.769-1.456a.75.75 0 0 1 .698 0l2.77 1.456-.53-3.084a.75.75 0 0 1 .216-.664l2.24-2.183-3.096-.45a.75.75 0 0 1-.564-.41L8 2.694Z\"></path>\n</svg>\n 307\n </a>\n <a href=\"/WangXuan95/FPGA-JPEG-LS-encoder/forks\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"forks\" role=\"img\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo-forked\">\n <path d=\"M5 5.372v.878c0 .414.336.75.75.75h4.5a.75.75 0 0 0 .75-.75v-.878a2.25 2.25 0 1 1 1.5 0v.878a2.25 2.25 0 0 1-2.25 2.25h-1.5v2.128a2.251 2.251 0 1 1-1.5 0V8.5h-1.5A2.25 2.25 0 0 1 3.5 6.25v-.878a2.25 2.25 0 1 1 1.5 0ZM5 3.25a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Zm6.75.75a.75.75 0 1 0 0-1.5.75.75 0 0 0 0 1.5Zm-3 8.75a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Z\"></path>\n</svg>\n 60\n </a>\n </p>\n ",
"\n <div class=\"d-flex width-full position-relative\">\n <div class=\"flex-1\">\n <svg aria-hidden=\"true\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo mr-1 color-fg-muted\">\n <path d=\"M2 2.5A2.5 2.5 0 0 1 4.5 0h8.75a.75.75 0 0 1 .75.75v12.5a.75.75 0 0 1-.75.75h-2.5a.75.75 0 0 1 0-1.5h1.75v-2h-8a1 1 0 0 0-.714 1.7.75.75 0 1 1-1.072 1.05A2.495 2.495 0 0 1 2 11.5Zm10.5-1h-8a1 1 0 0 0-1 1v6.708A2.486 2.486 0 0 1 4.5 9h8ZM5 12.25a.25.25 0 0 1 .25-.25h3.5a.25.25 0 0 1 .25.25v3.25a.25.25 0 0 1-.4.2l-1.45-1.087a.249.249 0 0 0-.3 0L5.4 15.7a.25.25 0 0 1-.4-.2Z\"></path>\n</svg>\n <span data-view-component=\"true\" class=\"position-relative\"><a data-hydro-click=\"{"event_type":"user_profile.click","payload":{"profile_user_id":20251744,"target":"PINNED_REPO","user_id":null,"originating_url":"https://github.com/WangXuan95"}}\" data-hydro-click-hmac=\"c81d2086fd934b5d3ed98bd3a15ac14ed0c4b8cdc9802ffa4ba66e381266e1cd\" id=\"461431074\" href=\"/WangXuan95/BSV_Tutorial_cn\" data-view-component=\"true\" class=\"Link mr-1 text-bold wb-break-word\"><span class=\"repo\">BSV_Tutorial_cn</span></a> <tool-tip data-direction=\"n\" id=\"tooltip-33da60d4-a691-4886-8ff9-1482b4e1f5ba\" for=\"461431074\" popover=\"manual\" data-type=\"label\" data-view-component=\"true\" class=\"sr-only position-absolute\">BSV_Tutorial_cn</tool-tip></span> <span></span><span class=\"Label Label--secondary v-align-middle mt-1 no-wrap v-align-baseline Label--inline\">Public</span>\n </div>\n </div>\n\n\n <p class=\"pinned-item-desc color-fg-muted text-small mt-2 mb-0\">\n 一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。\n </p>\n\n <p class=\"mb-0 mt-2 f6 color-fg-muted\">\n <span class=\"tmp-mr-3 d-inline-block\">\n <span class=\"repo-language-color\" style=\"background-color: #12223c\"></span>\n <span itemprop=\"programmingLanguage\">Bluespec</span>\n</span>\n\n <a href=\"/WangXuan95/BSV_Tutorial_cn/stargazers\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"stars\" role=\"img\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-star\">\n <path d=\"M8 .25a.75.75 0 0 1 .673.418l1.882 3.815 4.21.612a.75.75 0 0 1 .416 1.279l-3.046 2.97.719 4.192a.751.751 0 0 1-1.088.791L8 12.347l-3.766 1.98a.75.75 0 0 1-1.088-.79l.72-4.194L.818 6.374a.75.75 0 0 1 .416-1.28l4.21-.611L7.327.668A.75.75 0 0 1 8 .25Zm0 2.445L6.615 5.5a.75.75 0 0 1-.564.41l-3.097.45 2.24 2.184a.75.75 0 0 1 .216.664l-.528 3.084 2.769-1.456a.75.75 0 0 1 .698 0l2.77 1.456-.53-3.084a.75.75 0 0 1 .216-.664l2.24-2.183-3.096-.45a.75.75 0 0 1-.564-.41L8 2.694Z\"></path>\n</svg>\n 603\n </a>\n <a href=\"/WangXuan95/BSV_Tutorial_cn/forks\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"forks\" role=\"img\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo-forked\">\n <path d=\"M5 5.372v.878c0 .414.336.75.75.75h4.5a.75.75 0 0 0 .75-.75v-.878a2.25 2.25 0 1 1 1.5 0v.878a2.25 2.25 0 0 1-2.25 2.25h-1.5v2.128a2.251 2.251 0 1 1-1.5 0V8.5h-1.5A2.25 2.25 0 0 1 3.5 6.25v-.878a2.25 2.25 0 1 1 1.5 0ZM5 3.25a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Zm6.75.75a.75.75 0 1 0 0-1.5.75.75 0 0 0 0 1.5Zm-3 8.75a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Z\"></path>\n</svg>\n 53\n </a>\n </p>\n ",
"\n <div class=\"d-flex width-full position-relative\">\n <div class=\"flex-1\">\n <svg aria-hidden=\"true\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo mr-1 color-fg-muted\">\n <path d=\"M2 2.5A2.5 2.5 0 0 1 4.5 0h8.75a.75.75 0 0 1 .75.75v12.5a.75.75 0 0 1-.75.75h-2.5a.75.75 0 0 1 0-1.5h1.75v-2h-8a1 1 0 0 0-.714 1.7.75.75 0 1 1-1.072 1.05A2.495 2.495 0 0 1 2 11.5Zm10.5-1h-8a1 1 0 0 0-1 1v6.708A2.486 2.486 0 0 1 4.5 9h8ZM5 12.25a.25.25 0 0 1 .25-.25h3.5a.25.25 0 0 1 .25.25v3.25a.25.25 0 0 1-.4.2l-1.45-1.087a.249.249 0 0 0-.3 0L5.4 15.7a.25.25 0 0 1-.4-.2Z\"></path>\n</svg>\n <span data-view-component=\"true\" class=\"position-relative\"><a data-hydro-click=\"{"event_type":"user_profile.click","payload":{"profile_user_id":20251744,"target":"PINNED_REPO","user_id":null,"originating_url":"https://github.com/WangXuan95"}}\" data-hydro-click-hmac=\"c81d2086fd934b5d3ed98bd3a15ac14ed0c4b8cdc9802ffa4ba66e381266e1cd\" id=\"603678380\" href=\"/WangXuan95/NBLI\" data-view-component=\"true\" class=\"Link mr-1 text-bold wb-break-word\"><span class=\"repo\">NBLI</span></a> <tool-tip data-direction=\"n\" id=\"tooltip-ae08b325-4f27-4f36-a8d9-3bb9866364a9\" for=\"603678380\" popover=\"manual\" data-type=\"label\" data-view-component=\"true\" class=\"sr-only position-absolute\">NBLI</tool-tip></span> <span></span><span class=\"Label Label--secondary v-align-middle mt-1 no-wrap v-align-baseline Label--inline\">Public</span>\n </div>\n </div>\n\n\n <p class=\"pinned-item-desc color-fg-muted text-small mt-2 mb-0\">\n NBLI is a fast, better lossless image compression algorithm. The optimized version (fNBLI) can get 1.5x compression ratio, 8x faster encoding, and 1.2x faster decoding compared to PNG. It can also …\n </p>\n\n <p class=\"mb-0 mt-2 f6 color-fg-muted\">\n <span class=\"tmp-mr-3 d-inline-block\">\n <span class=\"repo-language-color\" style=\"background-color: #f34b7d\"></span>\n <span itemprop=\"programmingLanguage\">C++</span>\n</span>\n\n <a href=\"/WangXuan95/NBLI/stargazers\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"stars\" role=\"img\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-star\">\n <path d=\"M8 .25a.75.75 0 0 1 .673.418l1.882 3.815 4.21.612a.75.75 0 0 1 .416 1.279l-3.046 2.97.719 4.192a.751.751 0 0 1-1.088.791L8 12.347l-3.766 1.98a.75.75 0 0 1-1.088-.79l.72-4.194L.818 6.374a.75.75 0 0 1 .416-1.28l4.21-.611L7.327.668A.75.75 0 0 1 8 .25Zm0 2.445L6.615 5.5a.75.75 0 0 1-.564.41l-3.097.45 2.24 2.184a.75.75 0 0 1 .216.664l-.528 3.084 2.769-1.456a.75.75 0 0 1 .698 0l2.77 1.456-.53-3.084a.75.75 0 0 1 .216-.664l2.24-2.183-3.096-.45a.75.75 0 0 1-.564-.41L8 2.694Z\"></path>\n</svg>\n 91\n </a>\n <a href=\"/WangXuan95/NBLI/forks\" class=\"pinned-item-meta Link--muted\">\n <svg aria-label=\"forks\" role=\"img\" height=\"16\" viewBox=\"0 0 16 16\" version=\"1.1\" width=\"16\" data-view-component=\"true\" class=\"octicon octicon-repo-forked\">\n <path d=\"M5 5.372v.878c0 .414.336.75.75.75h4.5a.75.75 0 0 0 .75-.75v-.878a2.25 2.25 0 1 1 1.5 0v.878a2.25 2.25 0 0 1-2.25 2.25h-1.5v2.128a2.251 2.251 0 1 1-1.5 0V8.5h-1.5A2.25 2.25 0 0 1 3.5 6.25v-.878a2.25 2.25 0 1 1 1.5 0ZM5 3.25a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Zm6.75.75a.75.75 0 1 0 0-1.5.75.75 0 0 0 0 1.5Zm-3 8.75a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Z\"></path>\n</svg>\n 17\n </a>\n </p>\n "
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